ПОжалуйста, скажите,
что это за команды wrmsr и rdmsr...

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1.
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register. The high-order 32 bits are copied from EDX and the low-order 32 bits are copied from EAX. Always set the undefined or reserved bits in an MSR to the values previously read.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated, including the global entries (see "Translation Lookaside Buffers (TLBs)" in Chapter 3 of the IA-32 Intel® Architecture Software Developer's Manual, Volume 3). (MTRRs are an implementation-specific feature of the Pentium® Pro processor.)

The MSRs control functions for testability, execution tracing, performance monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be written to with this instruction and their addresses.

The WRMSR instruction is a serializing instruction (see "Serializing Instructions" in Chapter 7 of the IA-32 Intel® Architecture Software Developer's Manual, Volume 3).

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.


2.
Loads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit locations are undefined.

This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a general protection exception.

The MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors. Appendix B, Model-Specific Registers (MSRs), in the IA-32 Intel® Architecture Software Developer's Manual, Volume 3, lists all the MSRs that can be read with this instruction and their addresses.

The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1) before using this instruction.

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sniperZ, а откуда эта информация? Не подскажите, где скачать документацию по этой теме?..

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Necromancer13 пишет:
а откуда эта информация?

www.intel.com/products/processor/manuals/

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ы... спасибки=)
я скачаю всех их

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